h3-hip.c reimplements the GPU backend of antirez/h3.c in HIP. Pass HIP_ARCH=gfx1151, gfx90a, or gfx942 — the Makefile does not probe the GPU. Tagged v0.11.0.
MiniMax-H3 takes text, images, video and audio as one unified context and returns a clip with native stereo audio synthesized in the same forward pass as the pixels. Upstream h3.c is a native, dependency-light implementation of that stack for Apple Metal. This project keeps the host, model and CLI code and replaces the GPU layer with HIP.
One source tree, three HIP offload targets. The Makefile does not probe the GPU — you pass HIP_ARCH to match the product in the table.
| Product | HIP_ARCH | Architecture | Default DiT | SDPA | On this scoreboard |
|---|---|---|---|---|---|
| Strix Halo — Ryzen AI MAX+ 395 / Radeon 8060S | gfx1151 | RDNA, wave32 | INT8 + BF16 activations | rocWMMA | Yes — this SKU |
| Instinct MI210 | gfx90a | CDNA2, wave64 | BF16 GEMM | MFMA flash | Yes — this SKU |
| Instinct MI250 / MI250X | gfx90a | CDNA2, wave64 | same kernels as MI210 | MFMA flash | No — same ISA, not timed |
| Instinct MI300X | gfx942 | CDNA3, wave64 | BF16 GEMM | MFMA flash | Yes — this SKU |
Scoreboard columns are product SKUs we timed, not ISA names. gfx90a also builds for MI250 / MI250X; those numbers are not on this page. Build with make HIP_ARCH=gfx1151, gfx90a, or gfx942. CDNA INT8 DiT is opt-in (H3_INT8_MLP=1).
Two Halo milestones on Strix Halo, this port measured against itself. v0.9.0 is the kernel milestone. v0.11.0 then does two things: the Halo delta versus v0.9.0, and the same tree on MI210 and MI300X with a quality path and an opt-in speed path. Wall time moves with page-cache state; denoise GPU time (HIP events) is the figure to trust. Do not put MI210 / MI300X into the August multipliers.
Make the GPU cheap, then stop page-locking the 31 GiB host pool. After WMMA, short fox-s2 is no longer GPU-bound; the remaining wall clock is NVMe. This is the Halo performance milestone. MI210 / MI300X are not in these multipliers — they did not run the 18 Aug first profile.
Each rung is a dated Strix Halo session that kept something. Bar length is denoise GPU time; the number on the right is cumulative speedup against the first HIP profile. WMMA is the v0.9.0 milestone; the last rung is the v0.11.0 denoise on the same GPU.
Hand-written INT8 tiles topped out at roughly 4% of BF16 WMMA peak. That is why the v0.9.0 rung is not another tuning pass but an architecture change: move the hot kernels onto the matrix cores. After it, fox-s2 E2E stopped moving (~83–90 s, NVMe). v0.11.0 is a different job: INT8 workspace (denoise 6.4 s → 3.36 s), larger VAE tiles, and long T2VA — the clip that is still DiT-bound.
Same machine, same checkpoint, same quality-path CLI unless noted. fox-s2 E2E is still NVMe (~83–90 s), so it is not a speedup card. What moved is denoise and the 15 s cinematic. All-opts is opt-in (--token-reduction + INT8 VAE), not the tagged quality row.
v0.11.0 has two jobs besides the Halo-vs-v0.9.0 delta: ship the same tree on MI210 and MI300X, and publish both the default quality path and the opt-in speed path. Defaults: no --token-reduction. Halo DiT is INT8; CDNA DiT is BF16.
| Preset | Strix Halo (gfx1151) |
MI210 (gfx90a) |
MI300X (gfx942) |
|---|---|---|---|
| fox-s2 E2E | ~85–90 s (I/O) | ~10.8 s | ~16 s |
| fox-fast E2E | ~2 min (I/O) | ~18 s | ~12 s |
| 15 s cinematic E2E | 40 min 46 s | 12 min 11 s | 3 min 46 s |
Columns are the SKUs we timed: Strix Halo (gfx1151), MI210 (gfx90a), MI300X (gfx942). MI250 / MI250X also use HIP_ARCH=gfx90a; they are not these MI210 numbers. Quality path: default flags, no TR. v0.11.0 fox-s2 md5 34507f07… (512 px VAE tiles); v0.9.0 gate was 1731f95c…. Halo denoise: fox-s2 3.36 s · fox-fast 24.5 s. MI210 denoise: fox-s2 1.25 s · fox-fast 8.14 s. MI300X denoise: fox-s2 0.92 s · fox-fast 2.89 s.
Same 864×480 / 362-frame clip. Flags: --token-reduction plus H3_INT8_VAE=1. CDNA also uses H3_INT8_MLP=1 in the all-opts runs. Visible quality trade; not the gallery clip. GPU sampler is not a Halo 15 s win.
| 15 s cinematic | Strix Halo (gfx1151) |
MI210 (gfx90a) |
MI300X (gfx942) |
|---|---|---|---|
| Quality E2E | 40 min 46 s | 12 min 11 s | 3 min 46 s |
| Speed-path E2E | 27 min 3 s | 8 min 21 s | ~2.4 min |
| Speed-path denoise | 23 min 10 s | 6 min 56 s | 1 min 53 s |
| VAE peak (quality → speed) | 10.2 → 3.7 GiB | 10.2 → 3.7 GiB | 9.4 → 3.7 GiB |
Halo all-opts log. MI210 15 s all-opts E2E 501 s. MI300X all-opts denoise 113 s / E2E ~142 s. Full phase tables: PERFORMANCE.md.
All generated on the Strix Halo iGPU with the binary this page describes. H3 cannot render readable captions, so any on-screen title was composited with ffmpeg afterwards; the three clips marked untitled are raw model output.
MiniMax-H3 supports up to 362 aligned frames (~15 s at 24 fps). Same knobs on all three ISAs: --steps 20 --layers 45 --reuse 2, 864×480, seed 42. DiT denoise dominates; CDNA flash SDPA is why MI210 / MI300X drop the quality-path wall clock.
--token-reduction is opt-in (off by default; same flag as h3-spark.c). It pairs video tokens in middle DiT blocks so long-N SDPA shrinks. Faster; visible quality trade; not the gallery clip or the fox-s2 md5 path. Generate prints a stderr warning when the flag is on.
| Product | Path | Aligned frames | Duration | E2E wall | Denoise wall |
|---|---|---|---|---|---|
| Strix Halo (gfx1151) | quality | 362 | 15.1 s | 40 min 46 s | 36 min 38 s |
| Strix Halo (gfx1151) | --token-reduction | 362 | 15.1 s | 27 min 3 s | 23 min 10 s |
| MI210 (gfx90a) | quality | 362 | 15.1 s | 12 min 11 s | 10 min 47 s |
| MI210 (gfx90a) | --token-reduction | 362 | 15.1 s | 8 min 21 s | 6 min 56 s |
| MI300X (gfx942) | quality | 362 | 15.1 s | 3 min 46 s | 3 min 39 s |
| MI300X (gfx942) | all-opts / TR | 362 | 15.1 s | ~2.4 min | 1 min 53 s |
Timed SKUs only. Halo TR / all-opts: 27 min 3 s E2E, VAE peak 3.7 GiB (log). MI210 quality 12 min 11 s; speed path 8 min 21 s. MI300X quality 3 min 46 s / denoise 3 min 39 s; all-opts ~2.4 min / 113 s. Phase tables: PERFORMANCE.md.
# build for this GPU first make HIP_ARCH=gfx1151 -j$(nproc) h3 # or gfx90a # 864×480 · ~15 s (362 aligned frames) · fox-fast quality knobs ./h3 --profile -d /path/to/MiniMax-H3 \ -p "15 seconds, 16:9 landscape cinematic. A lone software engineer works late in a dim home office lit only by monitor glow and a desk lamp. Photoreal live-action feel with subtle handheld camera breathing. [0–3 seconds] Medium shot from behind the desk. Code scrolls on dual monitors; warm red accent light reflects on glass. Ambient: quiet keyboard clicks, soft fan hum, distant city rain. [3–6 seconds] Slow push-in over the shoulder. On screen, glowing matrix tiles and magenta wavefronts visualize a neural network training. The engineer pauses, sips coffee. Sound: gentle electronic pulse, a single soft notification chime. [6–9 seconds] Cut to close-up of hands typing, then rack focus to a small window showing a red fox walking through digital snow inside the monitor reflection. Sound: rising synthesized tone, subtle wind. [9–12 seconds] Smooth lateral move across the desk: terminal windows, GPU metrics, and a grid of video frames assembling on screen. Warm amber grade, volumetric dust in the lamp beam. [12–15 seconds] Controlled pullback reveals the full workspace at rest. The engineer leans back, satisfied. Sound: clean final impact, room tone fades. No readable text, no logos, no subtitles. Premium technology documentary aesthetic." \ --width 864 --height 480 --seconds 15 \ --steps 20 --layers 45 --reuse 2 --seed 42 \ -o outputs/long-15s-cinematic.mp4 # optional: --token-reduction + H3_INT8_VAE=1 (Halo 27 min 3 s / MI210 8 min 21 s / MI300X ~2.4 min) # append the flag to the same command; not the gallery / md5 path
Published video-diffusion acceleration usually attacks sequence length and step count, because on a datacenter GPU the transformer is the cost. On an integrated GPU with a carved-up memory map, the profile looks different: attention was expensive until the matrix cores were used properly, and after that the bottleneck moved to the SSD.
Tiled WMMA d128 SDPA; f32 linear and f32 d64 SDPA executed on the bf16 matrix cores; tiled f32 conv1d; a vectorized fused QKV + RoPE. The tiled-SDPA tail needed one writer per output row so results stay reproducible run to run.
Runtime INT8 quantization of the DiT weights with BF16 activations, driven through hipBLAS rather than hand-rolled sdot4 tiles, plus vectorized loads and a grouped packed FC2. Linear is still about 79% of fox-fast denoise GPU time, so this is where the remaining kernel headroom is.
free reports 31 GiB because the BIOS gave 96 GiB to VRAM. hipHostMalloc pins that small host pool; hipMalloc allocates from the carveout at roughly 90 GiB/s. Weights are now device-resident, uploaded through a recycled pinned staging buffer that retires after stream sync. AdaLN projections prefetch four blocks ahead and the video VAE loads on its own thread, both overlapping the disk.
make HIP_ARCH=gfx1151 -j$(nproc) h3 # or gfx90a # fox-s2 — the short A/B smoke, and the gfx1151 md5 gate ./h3 --profile -d /path/to/MiniMax-H3 \ -p "A red fox walks through fresh snow." \ --width 512 --height 512 --frames 22 \ --steps 2 --layers 35 --reuse 1 \ -o outputs/fox-s2.mp4 # fox-fast — upstream tutorial knobs, 11 DiT evaluations ./h3 --profile -d /path/to/MiniMax-H3 \ -p "A red fox walks through fresh snow in a pine forest. Medium tracking shot, natural winter light, realistic fur, soft footsteps and wind." \ --width 512 --height 512 --frames 22 \ --steps 20 --layers 45 --reuse 2 \ -o outputs/fox-fast.mp4